M68060 User's ManualMC68LC060 , and MC68EC060MC68LC060 , and MC68EC060 (collectively called M68060) consists of the M68060UM/AD, M68060 User's Manual, and the M68000PM/AD, M68000 Family Programmer's Reference Manual. The M68060 User's Manual describes the capabilities, operation, and programming of the M68060 superscalar 32-bit microprocessors. The M68000 Family Programmer's Reference Manual contains the complete instruction set for the M68000 family. The introduction of this manual includes general information concerning the MC68060 and summarizes the differences among the M68060 family devices. Additionally, appendices provide detailed information on how these M68060 derivatives operate differently from the MC68060. When reading this manual, disregard information concerning the floating-point unit in reference to the MC68LC060 , and disregard information concerning the floating-point unit and memory management unit in reference to the MC68EC060. The organization of this manual is as follows: Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Section 8 Section 9 Section 10 Section 11 Section 12 Section 13 Appendix A Appendix B Appendix C Appendix D Introduction Signal Description Integer Unit Memory Management Unit Caches Floating-Point Unit Bus Operation Exception Processing IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes Instruction Timings Applications Electrical and Thermal Characteristics Ordering Information and Mechanical Data MC68LC060 MC68EC060 MC68060 Software Package M68060 InstructionsMC68LC060 ................................................................................................ 1-3 MC68EC060 ............................................................................................... 1-3 Address Translation Differences .............................................................. 1-3 Instruction Differences .............................................................................. 1-3 Features........................................................................................................ 1-4 Architecture................................................................................................... 1-4 Processor Overview...................................................................................... 1-5 Functional Blocks........................................................................................ 1-5 Integer Unit ................................................................................................. 1-7 Instruction Fetch Unit................................................................................ 1-7 Integer Unit ............................................................................................... 1-8 Floating-Point Unit .................................................................................... 1-8 Memory Units ........................................................................................... 1-9 Address Translation Caches .................................................................... 1-9 Instruction and Data Caches .................................................................... 1-9 Cache Organization.............................................................................. 1-10 Cache Coherency................................................................................. 1-10 Bus Controller ........................................................................................... 1-10 Processing States ....................................................................................... 1-10 Programming Model.................................................................................... 1-11 Data Format Summary................................................................................ 1-14 Addressing Capabilities Summary .............................................................. 1-14 Instruction Set Overview ............................................................................. 1-15 Notational Conventions............................................................................... 1-21 Section 2 Signal Description 2.1 2.1.1 2.1.2 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5MC68LC060 , and MC68EC060 Pin Grid Array (RC Suffix) .... 13-2 MC68060, MC68LC060 , and MC68EC060 Quad Flat Pack (FE Suffix)... 13-3 Mechanical Data ......................................................................................... 13-4 Appendix A MC68LC060 Appendix B MC68EC060MC68LC060 , and MC68EC060. All three microprocessors offer superscalar integer performance of over 100 MIPS at 66 MHz. The MC68060 comes fully equipped with both a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control and desktop applications. For cost-sensitive embedded control and desktop applications where an MMU is required, but the additional cost of a FPU is not justified, the MC68LC060 offers high-performance at a low cost. Specifically designed for low-cost embedded control applications, the MC68EC060 eliminates both the FPU and MMU, permitting designers to leverage MC68060 performance while avoiding the cost of unnecessary features. Throughout this product brief, all references to the MC68060 also refer to the MC68LC060 and the MC68EC060, unless otherwise noted. Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architectural techniques, the MC68060 harnesses new levels of performance for the M68000 family. Incorporating 2.5 million transistors on a single piece of silicon, the MC68060 employs a deep pipeline, dual issue superscalar execution, a branch cache, a high-performance floating-point unit (MC68060 only), eight Kbytes each of on-chip instruction and data caches, and dual on-chip demand paging MMUs (MC68060 and MC68LC060 only). The MC68060 allows simultaneous execution of two integer instructions (or an integer and a float instruction) and one branch instruction during each clock. The MC68060 features a full internal Harvard architecture. The instruction and data caches are designed to support concurrent instruction fetch, operand read and operand write references on every clock. Separate 8-Kbyte instruction and 8-Kbyte data caches can be frozen to prevent allocation over time-critical code or data. The independent nature of the caches allows instruction stream fetches, data-stream fetches, and external accesses to occur simultaneously with instruction execution. The operand data cache is four-way banked to permit simultaneous read and write access each clock. A very high bandwidth internal memory system coupled with the compact nature of the M68000 family code allows the MC68060 to achieve extremely high levels of performance, even when operating from low-cost memory such as a 32-bit wide dynamic random access memory system. Instructions are fetched from the internal cache or external memory by a four-stage instruction fetch pipeline. The MC68060 variable-length instruction system is internally decoded into a fixed-length representation and channeled into an instruction buffer. The instruction buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetchMC68LC060 , and MC68EC060. The following paragraphs describe how the MC68LC060 and the MC68EC060 differ from the MC68060.MC68LC060 MC68LC060 is a derivative of the MC68060. The MC68LC060 has the same execution unit and MMU as the MC68060, but has no FPU. The MC68LC060 is 100% pin compatible with the MC68060. Disregard all information concerning the FPU when reading this manual. The following difference exists between the MC68LC060 and the MC68060: * The MC68LC060 does not contain an FPU. When floating-point instructions are encountered, a floating-point disabled exception is taken.,Dn ADD Dn, ADDA ,An ADDI #, ADDQ #, ADDX Dy,Dx ADDX -(Ay),-(Ax) AND ,Dn AND Dn, ANDI #, ANDI #,CCR ANDI #,SR ASd Dx,Dy1 ASd #,Dy ASd Bcc BCHG Dn, BCHG #, BCLR Dn, BCLR #, BFCHG {offset:width} BFCLR {offset:width} BFEXTS {offset:width},Dn BFEXTU {offset:width},Dn BFFFO {offset:width},Dn BFINS Dn,{offset:width} BFSET {offset:width} BFTST {offset:width} BKPT # BRA BSET Dn, BSET #, BSR BTST Dn, BTST #, CAS Dc,Du,,Dn CHK2 ,Rn CINVL , (An) CINVP , (An) CINVA CMP ,Dn CMPA ,An CMPI #, CMPM (Ay)+,(Ax)+ CMP2 ,Rn CPUSHL , (An) CPUSHP , (An) CPUSHA DBcc Dn, DIVS.W ,Dn32 / 16 16r:16q DIVS.L ,Dq32 / 32 32q DIVS.L ,Dr:Dq64 / 32 32r:32q2 DIVSL.L ,Dr:Dq 32 / 32 32r:32q DIVU.W ,Dn32 / 16 16r:16q DIVU.L ,Dq32 / 32 32q DIVU.L ,Dr:Dq64 / 32 32r:32q2 DIVUL.L ,Dr:Dq32 / 32 32r:32q EOR Dn, EORI #, EORI #,CCR EORI #,SR EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT.W Dnextend byte to word EXT.L L Dnextend word to long word EXTB.L Dn extend byte to long word FABS. ,FPn FABS.X FPm,FPn FABS.X FPn FrABS. ,FPn3 FrABS.X FPm,FPn3 FrABS.X FPn3 FADD. ,FPn FADD.X FPm,FPn FrADD. ,FPn3 FrADD.X FPm,FPn3 FBcc.SIZE FCMP. ,FPn FCMP.X FPm,FPn ,FPn FDIV.X FPm,FPn FrDIV. ,FPn3 FrDIV.X FPm,FPn3,FPn FINT.X FPm,FPn FINT.X FPn FINTRZ.,FPn FINTRZ.X FPm,FPn FINTRZ.X FPn FMOVE. ,FPn FMOVE. FPm, FMOVE.P FPm,{Dn} FMOVE.P FPm,{#k} FrMOVE. ,FPn3 FMOVE.L ,FPcr FMOVE.L FPcr, FMOVEM.X ,4 FMOVEM.X Dn, FMOVEM.X ,4 FMOVEM.X ,Dn FMOVEM.L ,5 FMOVEM.L ,5 FMUL. ,FPn FMUL.X FPm,FPn FrMUL ,FPn3 FrMUL.X FPm,FPn3 FNEG. ,FPn FNEG.X FPm,FPn FNEG.X FPn FrNEG. ,FPn3 FrNEG.X FPm,FPn3 FrNEG.X FPn3 FNOP FRESTORE FSAVE FScc.SIZE FSGLDIV. ,FPn FSGLDIV.X FPm,FPn FSGMUL. ,FPn FSGLMUL.X FPm, FPn FSQRT. ,FPn FSQRT.X FPm,FPn FSQRT.X FPn FrSQRT. ,FPn3 FrSQRT FPm,FPn3 FrSQRT FPn3 FSUB. ,FPn FSUB.X FPm,FPn FrSUB. ,FPn3 FrSUB.X FPm,FPn3 FTRAPcc FTRAPcc.W # FTRAPcc.L # FTST. FTST.X FPm ILLEGAL JMP An SP - 4 SP; An (SP) SP An, SP+d SP If supervisor state immediate data SR SR broadcast cycle STOP else TRAP Destination Shifted by count Destination Source Destination Source Destination CCR Destination Source CCR Syntax JSR LEA ,An LINK An,dn LSd Dx,Dy1 LSd #,Dy1 LSd 1 MOVE , MOVEA ,An MOVE CCR, MOVE ,CCR MOVE SR, MOVE ,SR MOVE USP,An MOVE An,USP MOVE16 (Ax)+, (Ay)+6 MOVE16 (xxx).L, (An) MOVE16 (An), (xxx).L MOVE16 (An)+, (xxx).L MOVEC Rc,Rn MOVEC Rn,Rc MOVEM ,4 MOVEM ,4 MOVEP Dx,(dn,Ay) MOVEP (dn,Ay),Dx MOVEQ #,Dn MOVES Rn, MOVES ,Rn MULS.W ,Dn 16 x 16 32 MULS.L ,Dl 32 x 32 32 MULS.L ,Dh-Dl 32 x 32 642 MULU.W ,Dn 16 x 16 32 MULU.L ,Dl 32 x 32 32 MULU.L ,Dh-Dl 32 x 32 642 NBCD NEG NEGX NOP NOT OR ,Dn OR Dn, ORI #, ORI #,CCR (SP) If supervisor state then invalidate instruction and data ATC entries for destination address else TRAP If supervisor state then logical address translate to physical address An else TRAP If supervisor state then Assert RSTO Line else TRAP Destination Rotated by count Destination Syntax ORI #,SR PACK -(Ax),-(Ay),#(adjustment) PACK Dx,Dy,#(adjustment) PEA PFLUSH (An) PFLUSHN (An) PFLUSHA PFLUSHAN PLPAR (An) PLPAW (An) RESET,Dy1 ROXd 1 RTD #(dn) RTE STOP # SUB ,Dn SUB Dn, SUBA ,An SUBI #, SUBQ #, SUBX Dx,Dy SUBX -(Ax),-(Ay) SWAP Dn TAS TRAP # TRAPcc TRAPcc.W # TRAPcc.L # TRAPV TST UNLK An UNPACK -(Ax),-(Ay),#(adjustment) UNPACK Dx,Dy,#(adjustment) tested sign-extended Single- And Double-Operand Operations Arithmetic addition or postincrement indicator. Arithmetic subtraction or predecrement indicator. Arithmetic multiplication. Arithmetic division or conjunction symbol. Invert; operand is logically complemented. Logical AND Logical OR Logical exclusive OR Source operand is moved to destination operand. Two operands are exchanged. Any double-operand operation. Operand is compared to zero and the condition codes are set appropriately. All bits of the upper portion are made equal to the high-order bit of the lower portion. Other Operations Equivalent to Format / Offset Word (SSP); SSP - 2 SSP; PC (SSP); SSP - 4 SSP; SR (SSP); SSP - 2 SSP; (Vector) PC Enter the stopped state, waiting for interrupts. The operand is BCD; operations are performed in decimal. Test the condition. If true, the operations after "then" are performed. If the condition is false and the optional "else" clause is present, the operations after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. Register Specification Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively. Base Register--An, PC, or suppressed. Data register D7-D0, used during compare. Data registers high- or low-order 32 bits of product. Any Data Register n (example: D5 is data register 5) Data register's remainder or quotient of divide. Data register D7-D0, used during update. Source and destination data registers, respectively. Any Memory Register n.10 If then else An Ax, Ay BR Dc Dh, Dl Dn Dr, Dq Du Dx, Dy MRn B, W, L D k P S X - inf # or # () [] bd dn LSB LSW MSB MSW od SCALE SIZE {offset:width} * C cc FC N U V X Z -- LB m m-n UB Any Address or Data Register Any source and destination registers, respectively. Index Register--An, Dn, or suppressed. Data Format and Type Positive Infinity Operand Data Format: Byte (B), Word (W), Long (L), Single (S), Double (D), Extended (X), or Packed (P). Specifies a signed integer data type (twos complement) of byte, word, or long word. Double-precision real data format (64 bits). A twos complement signed integer (-64 to +17) specifying a number's format to be stored in the packed decimal format. Packed BCD real data format (96 bits, 12 bytes). Single-precision real data format (32 bits). Extended-precision real data format (96 bits, 16 bits unused). Negative Infinity Subfields and Qualifiers Immediate data following the instruction word(s). Identifies an indirect address in a register. Identifies an indirect address in memory. Base Displacement Displacement Value, n Bits Wide (example: d16 is a 16-bit displacement). Least Significant Bit Least Significant Word Most Significant Bit Most Significant Word Outer Displacement A scale factor (1, 2, 4, or 8, for no-word, word, long-word, or quad-word scaling, respectively). The index register's size (W for word, L for long word). Bit field selection. Register Codes General Case. Carry Bit in CCR Condition Codes from CCR Function Code Negative Bit in CCR Undefined, Reserved for Motorola Use. Overflow Bit in CCR Extend Bit in CCR Zero Bit in CCR Not Affected or Applicable. Miscellaneous Effective Address Assemble Program Label List of registers, for example D3-D0. Lower Bound Bit m of an Operand Bits m through n of Operand Upper BoundMC68LC060 and Appendix B MC68EC060 for MC68LC060 and MC68EC060, respectively, identification field values. Bits 15-8--Revision Number Bits 15-8 contain the 8-bit device revision number. The first revision is 00000000. These bits are ignored when writing to the PCR. EDEBUG--Enable Debug Features When this bit is set, the MC68060 outputs internal control information on the address bus (A31-A0) and data bus (D31-D0) during idle bus cycles. This capability is implemented to support debug of designs that include the MC68060. When this bit is cleared, operation proceeds in a normal manner and no internal information is output on idle bus cycles. This bit is cleared at reset. Bits 6-2--Reserved by Motorola for future use and must always be zero. DFP--Disable Floating-Point Unit When this bit is set, the on-chip FPU is disabled and any attempt to execute a floatingpoint instruction generates a line F emulator exception. When this bit is cleared, the FPU executes all floating-point instructions. This bit is cleared at reset. Note that before this bit is set via the MOVEC instruction, an FNOP must be executed to ensure that all floatingpoint exceptions are caught and handled. This would prevent unexpected floating-point related exceptions to be reported when the FPU is re-enabled at a later time. ESS--Enable Superscalar Dispatch When this bit is set, the ability of the MC68060 to execute multiple instructions per machine cycle is enabled. When this bit is cleared, the ability to execute multiple instructions per cycle is disabled and the MC68060 operates at a slower rate with lower performance. This bit is cleared at reset.MC68LC060 or MC68EC060. Refer to Appendix A MC68LC060 and Appendix B MC68EC060 for details. Floating-point math refers to numeric calculations with a variable decimal point location. It is distinguished from integer math, which deals only with whole numbers and fixed decimal point locations. Historically, general-purpose microprocessors have had to depend on addon coprocessors and accelerators such as the MC68881/MC68882 for fast floating-point capabilities. The MC68060 features a built-in floating-point unit (FPU). Consolidating this important function on chip speeds up the overall processing and eliminates interfacing overhead required for external accelerators. The MC68060 FPU operates in parallel with the integer unit. The FPU does the numeric calculation while the integer unit performs other tasks. When used with Motorola-supplied emulation software, the M68060 software package (M68060SP), the MC68060 FPU is fully compliant with the ANSI/IEEE 754-1985 Standard for Binary Floating-Point Arithmetic. The on-chip FPU (shown in Figure 6-1) consists of four functional units: FPADD, FPMUL, FPDIV, and FPMISC. These functional units exist in parallel with the integer unit. The decode of floating-point operations is done in the same pipeline stage as integer instructions, and operands are fetched by the same logic which feeds the integer unit. The floatingpoint functional units are located in the primary pipeline of the integer unit. Only one floatingpoint functional unit at a time can be active. The FPU allows no concurrency between floating-point instructions to achieve a streamlined floating-point exception model. The FPADD unit performs floating-point addition and subtraction, compare, absolute value, negate, floating-point to integer and integer to floating-point conversions, and move-in and move-out of floating-point data when the precision and destination are not single, double, or extended precision. Results produced in this unit are rounded to the desired precision and rounding mode. The FPMUL unit performs floating-point multiply and rounding to desired precision and rounding mode. The FPDIV unit performs floating-point divide, square root, and move-in and move-out of floating-point data when the precision and destination are single, double, or extended precision. Results produced in the FDIV unit are rounded to the desired precision and rounding mode. The FPMISC unit handles the remaining functions within the FPU. This includes logic for FSAVE and FRESTORE, logic for FMOVEM, and exception logic. The floating-point control register (FPCR) and floating-point status register (FPSR) reside within this block. All of these functional units access the floating-point register file, which contains the program-visible register set., FMOVEM FPm, and FMOVE FPCR instructions do not affect the FPCC..X #immediate,FPn F.P #immediate,FPnMC68LC060 memory units and Appendix B MC68EC060 for information on the MC68EC060 memory unit.MC68LC060 memory units and Appendix B MC68EC060 for information on the MC68EC060 memory unit. The processor asserts TS during C1 to indicate the beginning of a bus cycle. If not already asserted from a previous bus cycle, TIP is also asserted at this time to indicate that a bus cycle is active. Clock 2 (C2) During C2, the processor negates TS. The selected device uses R/W and SIZx to place the data on the data bus. (The first transfer must supply the long word at the corresponding long-word boundary.) Concurrently, the selected device asserts TA and either negates TBI to indicate it can or asserts TBI to indicate it cannot support a burst transfer. The MC68060 implements a special mode called the acknowledge termination ignore state capability to aid in high-frequency designs. In this mode, the processor begins sampling termination signals such as TA after a user-programmed number of BCLK risingMC68LC060 memory units and Appendix B MC68EC060 for information on the MC68EC060 memory unit. Clock 2 (C2) During C2, the processor negates TS and drives the appropriate bytes of the data bus with the data to be written. All other bytes are driven with undefined values. The selected device uses R/W, SIZ1, SIZ0, A1, A0, or BS3-BS0, and CIOUT to register only the required information from the data bus. With the exception of R/W and CIOUT, these signals also select any or all of the bytes (D31-D24, D23-D16, D15-D8, and D7-D0). If C2 is not a wait state (CW), then the selected peripheral device asserts the TA signal. The MC68060 implements a special mode called the acknowledge termination ignore state capability to aid in high-frequency designs. In this mode, the processor begins the sampling of termination signals such as TA after a user-programmed number of BCLK rising edges has expired. The SAS signal is provided as a status output to indicate which BCLK rising edge the processor begins to sample the termination signals. If this mode is disabled, SAS is asserted during C2 to indicate that the processor immediately begins sampling the terminations signals. Refer to 7.14.1 Acknowledge Termination Ignore State Capability for details on this special mode. Assuming that the acknowledge termination ignore state capability is disabled, at the end of the C2, the processor samples the level of TA, terminating the bus cycle if TA is asserted. If TA is not recognized asserted at the end of the clock cycle, the processor ignores the data and inserts a wait state instead of terminating the transfer. The processor continues to sample TA on successive rising edges of BCLK until TA is recognized asserted. The data bus then three-states and the bus cycle ends. When the processor recognizes TA at the rising BCLK edge and terminates the bus cycle, TIP remains asserted if the processor is ready to begin another bus cycle. Otherwise, theMC68LC060 memory units and Appendix B MC68EC060 for information on the MC68EC060 memory unit. Clock 2 (C2) During C2, the processor negates TS and drives the data bus with the data to be written. The selected device uses R/W, SIZ1, SIZ0, or BSx to register the data on the data bus. Concurrently, the selected device asserts TA and either negates TBI to indicate it can or asserts TBI to indicate it cannot support a burst transfer. The MC68060 implements a special mode called the acknowledge termination ignore state capability to aid in high-frequency designs. In this mode, the processor begins sampling termination signals such as TA after a user-programmed number of BCLK rising edges has expired. The SAS signal is provided as a status output to indicate which BCLK rising edge the processor begins to sample the termination signals. If this mode is disabled, SAS is asserted during C2 to indicate that the processor immediately begins sampling the terminations signals. Refer to 7.14.1 Acknowledge Termination Ignore State Capability for details on this special mode. Assuming that the acknowledge termination ignore state capability is disabled, the processor samples the level of TA and TBI at end of C2. If TA is asserted, the transfer terminates. If TA is not recognized asserted, the processor inserts wait states instead of terminating the transfer. The processor continues to sample TA and TBI on successive rising edges of BCLK until TA is recognized asserted. If TBI was negated with the asser-MC68LC060 memory units and Appendix B MC68EC060 for information on the MC68EC060 memory unit. Clock 2 (C2) During C2, the processor negates TS. The selected device uses R/W, SIZ1, SIZ0, A1, and A0 or BSx, to place its information on the data bus. With the exception of R/W, these signals also select any or all of the data bus bytes (D24-D31, D16-D23, D15-D8, and D7- D0). Concurrently, the selected device asserts TA. At the end of the C2, assuming that the acknowledge termination ignore state capability is disabled, the processor samples the level of TA and registers the current value on the data bus. If TA is asserted, the read transfer terminates and the registered data is passed to the appropriate memory unit. If TA is not fetch and write-back stages of the integer unit pipeline perform accesses to the data memory unit. All read and write accesses are performed in strict program order. Compared with the MC68040, the MC68060 is always "serialized'. This feature makes it possible for automatic bus synchronization without requiring NOPs between instructions to guarantee serialization of reads and writes to I/O devices. The instruction restart model used for exception processing in the MC68060 may require special care when used with certain peripherals. After the operand fetch for an instruction, an exception that causes the instruction to be aborted can occur, resulting in another access for the operand after the instruction restarts. For example, an exception could occur after a read access of an I/O device's status register. The exception causes the instruction to be aborted and the register to be read again. If the first read accesses clears the status bits, the status information is lost, and the instruction obtains incorrect data., #imm,FPx), when the processor attempts to execute an FMOVEM.L #imm, instruction of more than one floating-point control register (FPCR, FPSR, FPIAR), when the processor attempts an FMOVEM.X instruction using a dynamic register list (FMOVEM.X Dn, or FMOVEM.X, ,Dn). The stack frame of type 0 is generated when this exception is reported. The stacked PC points to the logical address of the instruction that caused the exception. The FPIAR is unaffected. Refer to Section 6 Floating-Point Unit for details. An unimplemented A-line exception corresponds to vector number 10 and occurs when an instruction word pattern begins (bits 15-12) with $A. The A-line opcodes are user-reserved, and Motorola will not use any A-line instructions to extend the instruction set of any of Motorola's processors. A stack frame of format 0 is generated when this exception is reported. The stacked PC points to the logical address of the A-line instruction word. A floating-point unsupported data type exception occurs when the processor attempts to execute a bit pattern that it recognizes as an MC68881 instruction, the floating-point unit (FPU) is enabled via the processor configuration register (PCR), the floating-point instruction is implemented, but the floating-point data type is not implemented in the MC68060 FPU. This exception corresponds to vector number 55. A stack frame of type 0, 2, or 3 is generated when this exception is reported. The stacked PC points to the logical address of next instruction after the floating-point instruction. Refer to Section 6 Floating-Point Unit for details. A floating-point unimplemented instruction exception occurs when the processor attempts to execute an instruction word pattern that begins with $F, the processor recognizes this bit pattern as an MC68881 instruction, the FPU is enabled via the PCR, but the floating-point instruction is not implemented in the MC68060 FPU. This exception corresponds to vectorMC68LC060 or an MC68EC060. This exception corresponds to vector number 11 and shares this vector with the floating-point unimplemented and the F-line Unimplemented exceptions. A type 4 stack frame is generated when this exception is reported. The stacked PC points to the logical address of the next instruction. The PC of the faulted instruction field (SP+12) points to the floating-point instruction that needs to be emulated. The effective address field (SP+8) contains the effective address of the source or destination of the memory operand for the floating-point instruction. This field is valid only if the floating-point instruction references a memory operand. If the operand is in a register (either floating-point or data register), the effective address field contains $0. For the (An)+ and -(An) addressing modes, the address register is not modified by the processor, and it is the responsibility of the third party emulation software to modify the An value before returning to the user program. For the -(An) addressing mode, the value of the effective address field contains the address of the first memory operand except if the operand size is extended precision. For the extended precision case, the effective address field contains An-4 instead of An-12. This is a key difference between the MC68LC/EC060 and the MC68LC/EC040 stack frame, and third-party software emulators written for the MC68LC/EC040 must account for this difference. An unimplemented F-line exception occurs when an instruction word pattern begins (bits 15-12) with $F, the MC68060 does not recognize it as a valid F-line instruction (e.g., PTEST), and the processor does not recognize it as a floating-point MC68881 instruction. This exception corresponds to vector number 11 and shares this vector with the floatingpoint unimplemented instruction and the floating-point disabled exceptions. A stack frame of type 0 is generated by this exception. The stacked PC points to the logical address of the F-line word. If the processor encounters any other instruction word bit patterns that are not implemented by the MC68060, and is not covered by one of the other six unimplemented instruction exceptions, the illegal instruction exception is taken. The illegal instruction exception corresponds to vector number 4. An illegal instruction exception is also taken after a breakpoint acknowledge bus cycle is terminated, either by the assertion of the transfer acknowledge (TA) or the transfer error acknowledge (TEA) signal. An illegal instruction exception can also be a MOVEC instruction with an undefined register specification field in the first extension word. The M68000 instruction set defines the opcode $4AFC as an ILLEGAL instruction. This exception is also taken when that opcode is executed. A stack frame of type 0 is generated when this exception is taken. The stacked PC points to the logical address of the illegal instruction that caused the exception. for the floating-point instruction. * Instruction that caused the address error; Address field has the branch target address with A0=0. of memory operand (if any); PC of Faulted Instruction points to the F-line instruction word of the floatingpoint instruction. instruction, the memory operand is read, modified, and then written by this instruction. A read-modify-write does not imply a "locked" sequence. SIZE--Transfer Size 00 = Byte 01 = Word 10 = Long 11 = Double Precision or MOVE16 The SIZE field corresponds to the original access size. If a data cache line read results from a read miss and the line read encounters a bus error, the SIZE field in the resulting stack frame indicates the size of the original read generated by the execution unit. TT--Transfer Type This field defines the TT1-TT0 signal encoding for the faulted access. TM--Transfer Modifier This field defines the TM2-TM0 signal encoding for the faulted access. PBE--Push Buffer Bus Error 0 = Fault not caused by a bus error (TEA asserted) during a push buffer write. 1 = Fault caused by a bus error (TEA asserted) during a push buffer write. SBE--Store Buffer Bus Error 0 =Fault not caused by a bus error (TEA asserted) during a store buffer write. 1 =Fault caused by a bus error (TEA asserted) during a store buffer write. PTA--Pointer A Fault 0 =Fault not due to an invalid root level descriptor. 1 =Fault due to an invalid root level descriptor. PTB--Pointer B Fault 0 =Fault not due to an invalid pointer level descriptor. 1 =Fault due to an invalid pointer level descriptor. IL--Indirect Level Fault 0 =Fault not due to encountering a second indirect page descriptor. 1 =Fault due to encountering a second indirect page descriptor., in which the destination operand writes over the source operand. For these nonrecoverable write cases, the write reference has been lost and it is up to the system software designer to determine the next course of action. Probably the most prudent course of action is to discontinue the user program and enter a known supervisor state. The third step is to handle the transparent translation access error cases. This is indicated by TTR=1. All of these cases are recoverable as long as step two from above has been taken out. At this point, the access error may be caused by the following errors, which are mutually exclusive. * SP = 1 (supervisor protection violation detected by one of the four TTRs) * WP = 1 (write protection violation detected by one of the four TTRs) * RE = 1 (bus error on read) * WE = 1 (bus error on write) For the SP = 1 or WP = 1 cases, it is possible to modify the transparent translation descriptor to allow the access to occur once the instruction is restarted. For the RE = 1 or WE = 1 cases, unless the cause of the bus error is removed, when the instruction is restarted, the access error handler is re-entered, possibly resulting in an infinite loop. instruction. In this instruction, the processor fetches the memory operand, adds the contents of D0 internally, and writes the result out to memory. If the memory operand is misaligned and a bus error occurs on the second or later access, the first part of the memory operand would have been overwritten. If the instruction enters the access error exception handler, it cannot be restarted because original memory value has been corrupted. This read-modify-write instruction and others like it can be detected in the access error handler because the access error frame has separate read and write bits (RW field). If both bits are set, the instruction is a read-modify-write instruction similar to the ADD instruction case as discussed. Another non-recoverable write case is similar to the ADD case above, but is more difficult to detect. A MOVE , instruction in which the source operand and destination operand overlap may have the same problems as discussed in the ADD instruction if the destination operand is part of the source operand and a misaligned write occurs, which result in an access error on the second or later misaligned case. The MOVE , instruction is not normally considered a read-modify-write type of instruction, and is not detected simply by looking at the RW bits in the FSLW. An MC68060 system design could implement address/data capture logic to provide additional information for these bus error scenarios. instruction effectively appears as the extension word of the TRAPF. The BPE bit of the FSLW can be asserted if the instruction is a taken branch instruction, but the likelihood of this usage is expected to be very low. The replacement of branch instructions using this TRAPF construct is still recommended for cases where is not a branch instruction. It is the responsibility of the access error handler to test the BPE bit, and if asserted, clear the branch cache. Refer to 8.4.5 Recovering from an Access Error for details on how to recover from this error. = {(Ax), (Ax)+, -(Ax)}. Table 10-2. MC68060 Superscalar Classification of M680x0 Integer Instructions, BCLR Dy, BCLR #, BFCHG BFCLR Instruction Add Decimal with Extend Add Add Address Add Immediate " " Add Quick Add Extended AND Logical AND Immediate " " AND Immediate to Condition Codes Arithmetic Shift Left Arithmetic Shift Right Branch Conditionally Test a Bit and Change " Test a Bit and Clear " Test Bit Field and Change Test Bit Field and Clear Superscalar Classification pOEP-only pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-until-last pOEP | sOEP pOEP-only pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-until-last pOEP-only pOEP | sOEP pOEP | sOEP pOEP-only1 pOEP-only pOEP-until-last pOEP-only pOEP-until-last pOEP-only pOEP-only, BSR BTST Dy, BTST #, CAS CHK CLR CMP CMPA CMPI,Dx CMPI,-(Ax)+ Remaining CMPI CMPM DBcc DIVS.L DIVS.W DIVU.L DIVU.W EOR EORI,Dx EORI,-(Ax)+ Remaining EORI EORI to CCR EXG EXT EXTB.L ILLEGAL JMP JSR LEA LINK LSL LSR MOVE,Rx MOVE Ry, MOVE y,x MOVE #,x MOVEA MOVE from CCR Instruction Extract Bit Field Signed Extract Bit Field Unsigned Find First One in Bit Field Insert Bit Field Set Bit Field Test Bit Field Breakpoint Branch Always Test a Bit and Set " Branch to Subroutine Test a Bit " Compare and Swap with Operand Check Register Against Bounds Clear an Operand Compare Compare Address Compare Immediate " " Compare Memory Test Condition, Decrement and Branch Signed Divide Long Signed Divide Word Unsigned Long Divide Unsigned Divide Word Exclusive OR Logical Exclusive OR Immediate " " Exclusive OR Immediate to Condition Codes Exchange Registers Sign Extend Sign Extend Byte to Long Take Illegal Instruction Trap Jump Jump to Subroutine Load Effective Address Link and Allocate Logical Shift Left Logical Shift Right Move Data from Source to Destination " " " Move Address Move from Condition Codes Superscalar Classification pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP-until-last pOEP-only pOEP-only pOEP-until-last pOEP-only pOEP-only pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-until-last pOEP-until-last pOEP-only pOEP-only pOEP-only pOEP-only pOEP-only pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-until-last pOEP-only pOEP-only pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-only pOEP-only pOEP | sOEP pOEP-until-last pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP | sOEP pOEP-until-last pOEP-until-last pOEP | sOEP pOEP-onlyDm,FPn F&imm,FPn F.x,FPn which are classified as pOEP-only,a0Execute_result = a0 mov.l (a0),d0Base = a0 add.l d1,d0 Execute_result = d0 lea (a1,d0.l),a0Index = d0.l,Dx mov.l Dx,,d1 d0,d1 ,d0 d0,d1 Execute_result = d0 A = d0 Execute_result = d1 B = d1 Execute_result = d0 A = d0,d0 mov.l (a0,d0.l*4),d1,An ([bd,PC,Xn],o d) ([bd,PC],Xn,o d) Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Postincrement Address Register Indirect with Predecrement Address Register Indirect with Displacement Address Register Indirect with Index and Byte Displacement Address Register Indirect with Index and Base (16-, 32-bit) Displacement Memory Indirect Preindexed Mode Memory Indirect Postindexed Mode Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index and Byte Displacement Program Counter with Index and Base (16-, 32-bit) Displacement Immediate Program Counter Memory Indirect Preindexed Mode Program Counter Memory Indirect Postindexed Mode Calculation Time 0(0/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 1(0/0) 3(1/0) 3(1/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 1(0/0) 0(0/0) 3(1/0) 3(1/0) Dn 1(0/0) 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(0/0) An 1(0/0) 1(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(0/0) (An) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 1(0/1) (An)+ 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 1(0/1) -(An) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 1(0/1) Destination (d16,An) (d8,An,XiSF) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 3(1/1) 2(0/1) 2(0/1) (bd,An,XiSF) 2(0/1) 2(0/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(0/1) (xxx).WL 1(0/1) 1(0/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(1/1) 2(1/1) 2(1/1) 2(1/1) 3(1/1) 2(0/1)
